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AD9631/ad9632 ultralow distortion, wide bandwidth voltage feedback op amps a rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. features wide bandwidth AD9631, g = +1 ad9632, g = +2 small signal 320 mhz 250 mhz large signal (4 v p-p) 175 mhz 180 mhz ultralow distortion (sfdr), low noise ?13 dbc typ @ 1 mhz ?5 dbc typ @ 5 mhz ?2 dbc typ @ 20 mhz 46 dbm third order intercept @ 25 mhz 7.0 nv/ hz hz hz hz hz spectral noise density high speed slew rate 1300 v/ s settling 16 ns to 0.01%, 2 v step 3 v to 5 v supply operation 17 ma supply current applications adc input driver differential amplifiers if/rf amplifiers pulse amplifiers professional video dac current to voltage baseband and video communications pin diode receivers active filters/integrators/log amps general description the AD9631 and ad9632 are very high speed and wide bandwidth amplifiers. they are an improved performance alternative to the ad9621 and ad9622. the AD9631 is unity gain stable. the ad9632 is stable at gains of two or greater. using a voltage feedback architecture, the AD9631/ ad9632? exceptional set tling time, bandwidth, and low distortion meet the requirements of many applications that previously depended on current feedback amplifiers. its classical op amp structure works much more predictably in many designs. 8-lead plastic mini-dip (n), cerdip (q), and soic (r) packages 1 2 3 4 nc ?nput +input ? s top view 8 7 6 5 nc +v s output nc AD9631/ ad9632 nc = no connect a proprietary design architecture has produced an amplifier that combines many of the best characteristics of both current feed back and voltage feedback amplifiers. the AD9631 and ad 9632 exhibit exceptionally fast and accurate pulse response (16 ns to 0.01%) as well as extremely wide small signal and large signal bandwidth and ultralow distortion. the AD9631 achieves ?2 dbc at 20 mhz and 320 mhz small signal and 175 mhz large sig- nal bandwidths. these characteristics position the AD9631/ad9632 ideally for driving flash as well as high resolution adcs. additionally, the balanced high impedance inputs of the voltage feedback archi- tecture allow maximum flexibility when designing active filters. the AD9631 is offered in industrial (?0 c to +85 c) and mili- tary (?5 c to +125 c) temperature ranges and the ad9632 in industrial. industrial versions are available in plastic dip and soic, and military versions are packaged in cerdip. frequency ?hz ?0 10k harmonic distortion ?dbc 100k 1m 10m 100m ?0 ?0 ?0 ?10 ?30 second harmonic third harmonic v s = 5v r l = 500 v o = 2v p-p figure 1. AD9631 harmonic distortion vs. frequency, g = +1
rev. b ? AD9631/ad9632?pecifications AD9631a ad9632a parameter conditions min typ max min typ max unit dynamic performance bandwidth (? db) small signal v out 0.4 v p-p 220 320 180 250 mhz large signal 1 v out = 4 v p-p 150 175 155 180 mhz bandwidth for 0.1 db flatness v out = 300 mv p-p AD9631, r f = 140 w ; 130 130 mhz ad9632, r f = 425 w slew rate, average v out = 4 v step 1000 1300 1200 1500 v/ m s rise/fall time v out = 0.5 v step 1.2 1.4 ns v out = 4 v step 2.5 2.1 ns settling time to 0.1% v out = 2 v step 11 11 ns to 0.01% v out = 2 v step 16 16 ns harmonic/noise performance second harmonic distortion 2 v p-p; 20 mhz, r l = 100 w ?4 ?7 ?4 ?7 dbc r l = 500 w ?2 ?5 ?2 ?5 dbc third harmonic distortion 2 v p-p; 20 mhz, r l = 100 w ?6 ?9 ?4 ?7 dbc r l = 500 w ?1 ?4 ?1 ?4 dbc third order intercept 25 mhz 46 41 dbm noise figure r s = 50 w 18 14 db input voltage noise 1 mhz to 200 mhz 7.0 4.3 nv hz input current noise 1 mhz to 200 mhz 2.5 2.0 pa hz average equivalent integrated input noise voltage 0.1 mhz to 200 mhz 100 60 m v rms differential gain error (3.58 mhz) r l = 150 w 0.03 0.06 0.02 0.04 % differential phase error (3.58 mhz) r l = 150 w 0.02 0.04 0.02 0.04 degree phase nonlinearity dc to 100 mhz 1.1 1.1 degree dc performance 2 , r l = 150 w input offset voltage 3 310 25 mv t min ? max 13 8 mv offset voltage drift 10 10 m v/ c input bias current 2 7 2 7 m a t min ? max 10 10 m a input offset current 0.1 3 0.1 3 m a t min ? max 55 m a common-mode rejection ratio v cm = 2.5 v 70 90 70 90 db open-loop gain v out = 2.5 v 46 52 46 52 db t min ? max 40 40 db input characteristics input resistance 500 500 k w input capacitance 1.2 1.2 pf input common-mode voltage range 3.4 3.4 v output characteristics output voltage range, r l = 150 w 3.2 3.9 3.2 3.9 v output current 70 70 ma output resistance 0.3 0.3 w short circuit current 240 240 ma power supply operating range 3.0 5.0 6.0 3.0 5.0 6.0 v quiescent current 17 18 16 17 ma t min ? max 21 20 ma power supply rejection ratio t min ? max 50 60 56 66 db notes 1 see absolute maximum ratings and theory of operation sections of this data sheet. 2 m easured at a v = 50. 3 measured with respect to the inverting input. specifications subject to change without notice. electrical characteristics ( v s = 5 v; r load = 100 w ; a v = 1 (AD9631); a v = 2 (ad9632), unless otherwise noted.)
rev. b AD9631/ad9632 ? absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v voltage swing bandwidth product . . . . . . . . 550 v mhz internal power dissipation 2 plastic package (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 w small outline package (r) . . . . . . . . . . . . . . . . . . . . . . 0.9 w input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 v output short circuit duration . . . . . . . . . . . . . . . . . .o bserve power derating curves storage temperature range n, r . . . . . . . . . ?5 c to +125 c operating temperature range (a grade) . . . . 40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead plastic package: q ja = 90 c/w 8-lead soic package: q ja = 140 c/w metallization photo dimensions shown in inches and (millimeters) connect substrate to ? s AD9631 ad9632 ?n 2 +v s 7 6 out ?n 2 +v s 7 6 out 3 +in 4 ? s 3 +in 4 ? s 0.050 (1.27) 0.046 (1.17) 0.046 (1.17) maximum power dissipation the maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsu- lated devices is determined by the glass transition temperature of the plastic, approximately 150 c. exceeding this limit tem- porarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. ex ceeding a junction temperature of 175 c for an extended period can result in device failure. while the AD9631 and ad9632 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to ob serve the maximum power derating curves. ambient temperature ? c 2.0 1.5 0 ?0 maximum power dissipation ?w 1.0 0.5 ?0 ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 8-lead mini-dip package 8-lead soic package t j = +150 c figure 2. maximum power dissipation vs. temperature ordering guide temperature package package model range description option * AD9631an ?0c to +85 c plastic dip n-8 AD9631ar ?0 c to +85 c soic r-8 AD9631(smd) ?5 c to +125 c cerdip q-8 AD9631-eb evaluation board ad9632an ?0 c to +85 c plastic dip n-8 ad9632ar ?0 c to +85 c soic r-8 ad9632-eb evaluation board * n = plastic dip; q = cerdip; r= soic. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9631/ad9632 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. b ? AD9631/ad9632?ypical performance characteristics AD9631 0.1 f 10 f +v s 0.1 f 10 f ? s r f 130 v in r t 49.9 pulse generator t r /t f = 350ps r l = 100 v out tpc 1. AD9631 noninverting configuration, g = +1 1v 5ns tpc 2. AD9631 large signal transient response; v o = 4 v p-p, g = +1, r f = 250 w 100mv 5ns tpc 3. AD9631 small signal transient response; v o = 400 mv p-p, g = +1, r f = 140 w AD9631 0.1 f 10 f +v s 0.1 f 10 f ? s r f 130 r t 49.9 v in pulse generator t r /t f = 350ps 100 r l = 100 v out tpc 4. AD9631 inverting configuration, g = ? 1v 5ns tpc 5. AD9631 large signal transient response; v o = 4 v p-p, g = ?, r f = r in = 267 w 100mv 5ns tpc 6. AD9631 small signal transient response; v o = 400 mv p-p, g = ?, r f = r in = 267 w
rev. b AD9631/ad9632 ? ad9632 0.1 f 10 f +v s 0.1 f 10 f ? s r f 130 v in r t 49.9 pulse generator t r /t f = 350ps r l = 100 v out r in tpc 7. ad9632 noninverting configuration, g = +2 1v 5ns tpc 8. ad9632 large signal transient response; v o = 4 v p-p, g = +2, r f = r in = 422 w 100mv 5ns tpc 9. ad9632 small signal transient response; v o = 400 mv p-p, g = +2, r f = r in = 274 w ad9632 0.1 f 10 f +v s 0.1 f 10 f ? s r f 130 r t 49.9 v in pulse generator t r /t f = 350ps 100 r l = 100 v out tpc 10. ad9632 inverting configuration, g= ? 1v 5ns tpc 11. ad9632 large signal transient response; v o = 4 v p-p, g = ?, r f = r in = 422 w , r t = 56.2 w 100mv 5ns tpc 12. ad9632 small signal transient response; v o = 400 mv p-p, g = ?, r f = r in = 267 w , r t = 61.9 w
rev. b ? AD9631/ad9632 frequency ?hz 1 1m gain ?db 10m 100m 1g v s = 5v r l = 100 v o = 300mv p-p 0 ? ? ? ? ? ? ? ? ? r f 50 r f 200 r f 100 r f 150 tpc 13. AD9631 small signal frequency response, g = +1 frequency ?hz 0.1 1m gain ?db 10m 100m 0 ?.1 ?.2 ?.3 ?.4 ?.5 ?.6 ?.7 ?.8 ?.9 500m r f 140 r f 100 r f 150 v s = 5v r l = 100 g = +1 v o = 300mv p-p r f 120 tpc 14. AD9631 0.1 db flatness, n package (for r package add 20 w to r f ) 90 gain ?db 80 70 60 50 40 30 20 10 0 ?0 ?0 frequency ?hz 10k 100k 1m 1g 10m 100m 100 20 0 ?0 40 60 80 ?0 ?00 ?0 ?0 phase margin ?degrees ?20 phase gain tpc 15. AD9631 open-loop gain and phase margin vs. frequency, r l = 100 w va lue of feedback resistor ( r f ) ? 20 ?db bandwidth ?mhz 40 60 80 450 400 350 300 250 100 120 140 160 180 200 220 240 v s = 5v r l = 100 gain = +1 n package r package AD9631 r l 130 r f tpc 16. AD9631 small signal ? db bandwidth vs. r f frequency ?hz 1 1m 10m 100m 0 ? ? ? ? ? ? ? ? ? 500m output ?db r f 250 r f = 50 to 250 by 50 v s = 5v r l = 100 v o = 4v p-p tpc 17. AD9631 large signal frequency response, g = +1 frequency ?hz 1 1m gain ?db 10m 100m 1g 0 ? ? ? ? ? ? ? ? ? v s = 5v r l = 100 v o = 300mv p-p r f 267 tpc 18. AD9631 small signal frequency response, g = ?
rev. b AD9631/ad9632 ? frequency ?hz ?0 10k harmonic distortion ?dbc 100k 1m 10m ?0 ?0 ?0 ?10 ?30 100m v s = 5v r l = 500 g = +1 v o = 2v p-p third harmonic second harmonic tpc 19. AD9631 harmonic distortion vs. frequency, r l = 500 w frequency ?hz ?0 10k harmonic distortion ?dbc 100k 1m 10m ?0 ?0 ?0 ?10 ?30 100m v s = 5v r l = 100 g = +1 v o = 2v p-p third harmonic second harmonic tpc 20. AD9631 harmonic distortion vs. frequency, r l = 100 w frequency ?mhz 60 10 intercept ?dbm 20 30 40 55 50 45 35 30 100 50 60 70 80 90 40 25 20 tpc 21. AD9631 third order intercept vs. frequency 0.10 1st 11th 6th diff gain ?% 0.05 0.00 ?.05 ?.10 2nd 7th 3rd 8th 4th 9th 5th 10th 0.00 ?.05 ?.10 0.10 diff phase ?degrees 1st 11th 6th 2nd 7th 3rd 8th 4th 9th 5th 10th 0.05 tpc 22. AD9631 differential gain and phase error, g = +2, r l = 150 w settling time ? ns 0.3 0 error ?% 10 20 30 0.2 0.1 0.0 ?.2 ?.3 40 50 60 70 80 ?.1 tpc 23. AD9631 short-term settling time, 2 v step, r l = 100 w settling time ? s 0.3 0 error ?% 123 0.2 0.1 0.0 ?.2 45678 ?.1 910 tpc 24. AD9631 long-term settling time, 2 v step, r l = 100 w
rev. b ? AD9631/ad9632 frequency ?hz 7 1m gain ?db 10m 100m 1g v s = 5v r l = 100 v o = 300mv p-p 6 5 4 3 2 1 0 ? ? ? r f 225 r f 125 r f 425 r f 325 tpc 25. ad9632 small signal frequency response, g = +2 frequency ?hz 0.1 1m output ?db 10m 100m 0 ?.1 ?.2 ?.3 ?.4 ?.5 ?.6 ?.7 ?.8 ?.9 v s = 5v r l = 100 g = +2 v o = 300mv p-p r f 325 r f 275 r f 375 r f 425 tpc 26. ad9632 0.1 db flatness, n package (for r package add 20 w to r f ) 65 a ol ?db 60 55 50 45 40 35 30 25 20 15 10 frequency ?hz 10k 100k 1m 1g 10m 100m 50 0 100 ?50 ?00 ?00 ?0 phase ?degrees ?50 5 0 ? ?0 ?5 phase gain tpc 27. ad9632 open-loop gain and phase margin vs. frequency, r l = 100 w va l u e of r f , r in ? 100 ?db bandwidth ?mhz 150 200 250 350 300 250 200 150 300 350 400 450 500 550 v s = 5v r l = 100 gain = +2 ad9632 r l 100 49.9 r in r f n package r package tpc 28. ad9632 small signal ? db bandwidth vs. r f , r in frequency ?hz 7 1m 10m 100m 6 5 4 3 2 1 0 ? ? ? 500m output ?db r f 525 r f = 125 to 525 by 100 v s = 5v r l = 100 v o = 4v p-p tpc 29. ad9632 large signal frequency response, g = +2 frequency ?hz 1 1m gain ?db 10m 100m 1g 0 ? ? ? ? ? ? ? ? ? v s = 5v r l = 100 v o = 300mv p-p r f , r in 267 tpc 30. ad9632 small signal frequency response, g = ?
rev. b AD9631/ad9632 ? frequency ?hz ?0 10k harmonic distortion ?dbc 100k 1m 10m ?0 ?0 ?0 ?10 ?30 100m v s = 5v r l = 500 g = +2 v o = 2v p-p third harmonic second harmonic tpc 31. ad9632 harmonic distortion vs. frequency, r l = 500 w frequency ?hz ?0 10k harmonic distortion ?dbc 100k 1m 10m ?0 ?0 ?0 ?10 ?30 100m v s = 5v r l = 100 g = +2 v o = 2v p-p third harmonic second harmonic tpc 32. ad9632 harmonic distortion vs. frequency, r l = 100 w frequency ?mhz 50 10 intercept ?dbm 20 30 40 45 40 35 25 20 100 50 60 70 80 90 30 15 10 tpc 33. ad9632 third order intercept vs. frequency 0.04 1st 11th 6th diff gain ?% 0.02 0.00 ?.02 ?.04 2nd 7th 3rd 8th 4th 9th 5th 10th 0.00 ?.02 ?.04 0.04 diff phase ?degrees 1st 11th 6th 2nd 7th 3rd 8th 4th 9th 5th 10th 0.02 tpc 34. ad9632 differential gain and phase error g = +2, r l = 150 w settling time ? ns 0 error ?% 10 20 30 0.2 0.1 0.0 ?.2 ?.3 40 50 60 70 80 ?.1 tpc 35. ad9632 short-term settling time, 2 v step, r l = 100 w settling time ? s 0.3 0 error ?% 123 0.2 0.1 0.0 ?.2 45678 ?.1 910 tpc 36. ad9632 long-term settling time, 2 v step, r l = 100 w
rev. b ?0 AD9631/ad9632 frequency ?hz 24 10 input noise voltage ?nv/ hz 100 1k 10k 21 18 15 12 9 100k 6 3 v s = 5v tpc 37. AD9631 noise vs. frequency 80 psrr ?db 75 70 65 60 55 50 45 40 35 30 25 frequency ?hz 10k 100k 1m 1g 10m 100m 20 15 10 5 0 ?srr + psrr tpc 38. AD9631 psrr vs. frequency frequency ?hz 100 100k cmrr ?db 1m 10m 100m 90 80 70 60 50 1g 40 30 20 v s = 5v v cm = 1v r l = 100 tpc 39. AD9631 cmrr vs. frequency frequency ?hz 17 10 input noise voltage ?nv/ hz 100 1k 10k 15 13 11 9 7 100k 5 3 v s = 5v tpc 40. ad9632 noise vs. frequency 80 psrr ?db 75 70 65 60 55 50 45 40 35 30 25 frequency ?hz 10k 100k 1m 1g 10m 100m 20 15 10 5 0 ?srr + psrr tpc 41. ad9632 psrr vs. frequency frequency ?hz 100 100k cmrr ?db 1m 10m 100m 90 80 70 60 50 1g 40 30 20 v s = 5v v cm = 1v r l = 100 tpc 42. ad9632 cmrr vs. frequency
rev. b AD9631/ad9632 ?1 frequency ?hz 1000 10k r out ? 100k 1m 10m 100 10 1 0.1 0.01 100m v s = 5v gain = +1 tpc 43. AD9631 output resistance vs. frequency frequency ?hz 1000 10k r out ? 100k 1m 10m 100 10 1 0.1 0.01 100m v s = 5v gain = +1 tpc 44. ad9632 output resistance vs. frequency junction temperature ? c ?0 output swing ?v ?0 ?0 0 4.1 4.0 3.9 3.7 3.6 20 40 60 80 100 3.8 3.5 3.4 3.3 120 140 v s = 5v r l = 150 r l = 50 +v out ? out +v out ? out tpc 45. AD9631/ad9632 output swing vs. temperature junction temperature ? c ?0 open-loop gain ?v/v ?0 ?0 0 1350 1250 1150 950 850 20 40 60 80 100 1050 750 650 550 120 140 450 350 ad9632 AD9631 +a ol ? ol +a ol ? ol tpc 46. open-loop gain vs. temperature junction temperature ? c ?0 psrr ?db ?0 ?0 0 76 74 72 68 66 20 40 60 80 100 70 64 62 60 120 140 58 56 ?srr + psrr ?srr + psrr ad9632 AD9631 ad9632 AD9631 tpc 47. psrr vs. temperature junction temperature ? c ?0 cmrr ?db ?0 ?0 0 98 96 94 90 88 20 40 60 80 100 92 86 120 140 +cmrr ?mrr tpc 48. AD9631/ad9632 cmrr vs. temperature
rev. b ?2 AD9631/ad9632 junction temperature ? c ?0 supply current ?ma ?0 ?0 0 21 20 19 17 16 20 40 60 80 100 18 15 120 140 14 ad9632 AD9631 6v 5v 6v 5v ad9632 AD9631 tpc 49. supply current vs. temperature junction temperature ? c ?0 input offset voltage ?mv ?0 ?0 0 ?.0 ?.5 ?.0 ?.0 ?.5 20 40 60 80 100 ?.5 ?.0 120 140 ?.5 ad9632 AD9631 ?.0 v s = 5v v s = 6v v s = 5v v s = 6v tpc 50. input offset voltage vs. temperature input offset voltage ?mv ? count ? ? ? 220 200 180 140 120 ? ? ? 0 1 160 100 23 80 60 4567 40 20 0 100 90 80 70 60 50 40 30 20 10 0 percent cumulative freq. dist 3 wafer lots count = 1373 tpc 51. AD9631 input offset voltage distribution junction temperature ? c ?0 short circuit current ?ma ?0 ?0 0 250 240 230 210 200 20 40 60 80 100 220 190 120 140 180 ad9632 AD9631 sink source sink source tpc 52. short circuit current vs. temperature junction temperature ? c ?0 input bias current ? a ?0 ?0 0 2.0 1.5 1.0 0.0 ?.5 20 40 60 80 100 0.5 ?.0 120 140 ?.5 ad9632 AD9631 ?.0 ? b +i b ? b +i b tpc 53. input bias current vs. temperature input offset voltage ?mv ? count ? ? ? 180 140 120 ? ? ? 0 1 160 100 23 80 60 4567 40 20 0 100 90 80 70 60 50 40 30 20 10 0 percent 3 wafer lots count = 573 cumulative freq. dist tpc 54. ad9632 input offset voltage distribution
?3 rev. b AD9631/ad9632 theory of operation general the AD9631 and ad9632 are wide bandwidth, voltage feedback amplifiers. since their open-loop frequency response follows the conventional 6 db/octave roll-off, their gain bandwidth prod uct is basically constant. increasing their closed-loop gain results in a corresponding decrease in small signal bandwidth. this can be observed by noting the bandwidth specification between the AD9631 (gain of +1) and ad 9632 (gain of + 2). t he AD9631/ ad9632 typically maintain 65 degrees of phase margin. this high margin minimizes the effects of signal and noise peak ing. feedback resistor choice the value of the feedback resistor is critical for optimum perfor- mance on the AD9631 (gain of +1) and less critical as the gain increases. therefore, this section is specifically targeted at the AD9631. at minimum stable gain (+1), the AD9631 provides optimum dynamic performance with r f = 140 w . this resistor acts only as a parasitic suppressor against damped rf oscillations that can occur due to lead (input, feedback) inductance and parasitic capacitance. this value of r f provides the best combination of wide bandwidth, low parasitic peaking, and fast settling time. in fact, for the same reasons, a 100 w ?30 w resistor should be placed in series with the positive input for other AD9631 noninverting and all AD9631 inverting configurations. the correct connection is shown in figures 3 and 4. AD9631/ ad9632 +v s ? s 100 ?30 r term r in v in r g 0.1 f 10 f 0.1 f 10 f r f v out g = 1 + r f r g figure 3. noninverting operation AD9631/ ad9632 +v s ? s 100 ?30 r term r in r g 0.1 f 10 f 0.1 f 10 f r f v out v in g = ? r f r g figure 4. inverting operation when the AD9631 is used in the transimpedance (i to v) mode, such as in photodiode detection, the value of r f and diode capacitance ( c i ) are usually known. generally, the value of r f selected will be in the k w range, and a shunt capacitor ( c f ) across r f will be required to maintain good amplifier stability. the value of c f required to maintain optimal flatness (<1 db peaking) and settling time can be estimated as: ccr r foif of @ () [] 21 22 1 2 ?/ where w o is equal to the unity gain bandwidth product of the amplifier in rad/sec, and c i is the equivalent total input capacitance at the inverting input. typically w o = 800 10 6 rad/sec (see tpc 15). as an example, choosing r f = 10 k w and c i = 5 pf requires c f to be 1.1 pf (note: c i includes both source and parasitic circuit capacitance). the bandwidth of the amplifier can be estimated using the c f calculated as: f rc d ff 3 16 2 @ . AD9631 r f v out c i i i c f figure 5. transimpedance configuration for general voltage gain applications, the amplifier bandwidth can be closely estimated as: f rr d o fg 3 21 @ + () / this estimation loses accuracy for gains of +2/? or lower, due to the amplifier? damping factor. for these ?ow gain?cases, the bandwidth will actually extend beyond the calculated value (see tpcs 13 and 25). as a rule of thumb, capacitor c f will not be required if: rr c ng f g i o () 4 where ng is the noise gain (1 + r f / r g ) of the circuit. for most voltage gain applications, this should be the case.
?4 rev. b AD9631/ad9632 pulse response unlike a traditional voltage feedback amplifier, where the slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the AD9631 and ad9632 provide ?n dem and current that increases proportionally to the input ?tep?signal amplitude. this results in slew rates (1300 v/ m s) comparable to wideband current feedback designs. this, combined with relatively low input noise current (2.0 pa/ hz ), gives the ad 9631 and ad9632 the best attributes of both voltage and current feedback amplifiers. large signal performance the outstanding large signal operation of the AD9631 and ad9632 is due to a unique, proprietary design architecture. in order to maintain this level of performance, the maximum 550 v-mhz product must be observed (e.g., @ 100 mhz, v o 5.5 v p-p). power supply bypassing adequate power supply bypassing can be critical when optimiz- ing the performance of a high frequency circuit. inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier? response. in addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 m f) will be required to provide the best settling time and lowest distortion. a parallel combination of at least 4.7 m f, and between 0.1 m f and 0.01 m f, is recomm ended. some brands of electrolytic capacitors will require a small series damping resistor a 4.7 w for optimum results. driving capacitive loads the AD9631 and ad9632 were designed primarily to drive nonreactive loads. if driving loads with a capacitive component is desired, the best frequency response is obtained by the addi tion of a small series resistance as shown in figure 6. the accompanying graph shows the optimum value for r series versus capacitive load. it is worth noting that the frequency response of the cir- cuit when driving large capacitive loads will be dominated by the passive roll-off of r series and c l . AD9631/ ad9632 r f c l r in r in r l 1k r series figure 6. driving capacitive loads c l ?pf 0 r series ? 51015 40 30 20 20 25 10 figure 7. recommended r series vs. capacitive load applications the AD9631 and ad9632 are voltage feedback amplifiers well suited for applications such as photodetectors, active filters, and log amplifiers. the devices?wide bandwidth (320 mhz), phase margin (65 ), low noise current (2.0 pa/ hz ), and slew rate (1300 v/ m s) give higher performance capabilities to these appli- cations over previous voltage feedback designs. with a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the devices are an excellent choice for dac i/v conversion. the same characteristics along with low harmonic distortion make them a good choice for adc buffering/amplification. with superb linear- ity at relatively high signal frequencies, the AD9631 and ad9632 are ideal drivers for adcs up to 12 bits. operation as a video line driver the AD9631 and ad9632 have been designed to offer outstanding performance as video line drivers. the important specifications of differential gain (0.02%) and differential phase (0.02 ) meet the most exacting hdtv demands for driving video loads. 75 0.1 f AD9631/ ad9632 +v s ? s 274 10 f v out 0.1 f 10 f 274 v in 75 cable 75 cable 75 75 figure 8. video line driver
rev. b AD9631/ad9632 ?5 active filters the wide bandwidth and low distortion of the AD9631 and ad9632 are ideal for the realization of higher bandwidth active filters. these characteristics, while being more common in many current feedback op amps, are offered in the AD9631 and ad9632 in a voltage feedback configuration. many active filter configurations are not realizable with current feedback amplifiers. a multiple feedback active filter requires a voltage feedback amplifier and is more demanding of op amp performance than other active filter configurations, such as the sallen-key. in g eneral, the amplifier should have a bandwidth that is at least 10 times the bandwidth of the filter if problems due to phase shift of the amplifier are to be avoided. figure 9 is an example of a 20 mhz low-pass multiple feedback active filter using an ad9632. ?v 10 f 0.1 f 0.1 f +5v 10 f ad9632 100 c1 50pf r3 78.7 r4 154 c2 100pf r1 154 v in v out figure 9. active filter circuit choose: f o = cutoff frequency = 20 mhz a = damping ratio = 1/ q = 2 h = absolute value of circuit gain = r 4 r 1 = 1 then: kfc c ch r hk r kh rhr o = = + = = + = 21 2 41 1 1 2 3 21 41 () () () 2 a/d converter driver as a/d converters move toward higher speeds with higher reso- lutions, there becomes a need for high performance drivers that will not degrade the analog signal to the converter. it is desir- able from a system? standpoint that the a/d be the element in the signal chain that ultimately limits overall distortion. this places new demands on the amplifiers that are used to drive fast, high resolution a/ds. with high bandwidth, low distortion, and fast settling time, the AD9631 and ad9632 make high performance a/d drivers for advanced converters. figure 10 is an example of an AD9631 used as an input driver for an ad872, a 12-bit, 10 msps a/d converter. ?v analog 10 f 0.1 f 0.1 f +5v analog 10 f AD9631 140 130 av dd a gnd 0.1 f 4 5 +5v analog v ina 1 2 27 28 v inb ref gnd 0.1 f ref in 26 ref out 1 f av ss av ss dv dd dgnd 10 0.1 f 7 6 +5v digital clk msb bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 a gnd dv dd dgnd 0.1 f 22 23 +5v digital 21 20 otr 19 18 17 16 15 14 13 12 11 10 9 8 49.9 digital output 0.1 f 0.1 f ?v analog 325 ad872 clock input analog in figure 10. AD9631 used as driver for an ad872, a 12-bit, 10 msps a/d converter
rev. b ?6 AD9631/ad9632 layout considerations the specified high speed performance of the AD9631 and ad9632 requires careful attention to board layout and com- po nent selection. proper rf design techniques and low-pass parasitic component selection are mandatory. the pcb should have a ground plane covering all unused por tions of the component side of the board to provide a low impedance path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply bypassing (see figure 10). one end should be connected to the ground plane and the other within 1/8 inch of each power pin. an additional large (0.47 m f?0 m f) tantalum electrolytic capacitor should be connected in parallel, though not necessarily so close, to supply current for fast, large signal changes at the output. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance variations of less than 1 pf at the in verting input will significantly affect high speed performance. stripline design techniques should be used for long signal traces (greater than about 1 inch). these should be designed with a characteristic impedance of 50 w or 75 w and be properly termi- nated at each end. evaluation board evaluation boards for both the AD9631 and ad9632 are avail- able that have been carefully laid out and tested to demonstrate that the specified high speed performance of the devices can be realized. for ordering information, please refer to the ordering guide. the layout of the evaluation board can be used as shown or serve as a guide for a board layout. table i. AD9631 ad9632 gain gain component ? +1 +2 +10 +100 ? +2 +10 +100 r f 274 w 140 w 274 w 2 k w 2 k w 274 w 274 w 2 k w 2 k w r g 274 w 274 w 221 w 20.5 w 274 w 274 w 221 w 20.5 w r o (nominal) 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w 100 w 100 w 49.9 w 49.9 w r s 100 w 130 w 100 w 100 w 100 w 100 w 100 w 100 w 100 w r t (nominal) 61.9 w 49.9 w 49.9 w 49.9 w 49.9 w 61.9 w 49.9 w 49.9 w 49.9 w small signal bw (mhz) 90 320 90 10 1.3 250 250 20 3 +v s r f r g r s r t r o ? s out in inverting configuration +v s r f r g r s r t r o ? s out in noninverting configuration optional ? s +v s c1 1000pf c3 0.1 f c5 10 f c2 1000pf c4 0.1 f c6 10 f supply bypassing figure 11. inverting and noninverting configurations for evaluation boards
rev. b AD9631/ad9632 ?7 soic (r) noninverter figure 12. evaluation board silkscreen (top) soic (r) noninverter figure 13. board layout (solder side) soic (r) noninverter figure 14. board layout (component side)
rev. b ?8 AD9631/ad9632 outline dimensions 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa 8-lead ceramic dip?lass hermetic seal [cerdip] (q-8) dimensions shown in inches and (millimeters) 1 4 85 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 8-lead plastic dual-in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095aa
rev. b AD9631/ad9632 ?9 revision history location page 1/03?ata sheet changed from rev. a to rev. b. deleted dip (n) inverter, soic (r) inverter, and dip (n) noninverter evaluation boards in figures 12?4 . . . . . . . . . . . . . . . 17 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
c00601??/03(b) printed in u.s.a. ?0

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